Make your own free website on Tripod.com
Blog Tools
Edit your Blog
Build a Blog
View Profile
« July 2017 »
S M T W T F S
1
2 3 4 5 6 7 8
9 10 11 12 13 14 15
16 17 18 19 20 21 22
23 24 25 26 27 28 29
30 31
You are not logged in. Log in
Entries by Topic
All topics  «
Assignment 2
Carl Love (IBM)
Guest Speaker
Requirements and Use Case
week 3
week 4
Senior Project
Wednesday, 2 February 2005
memory perfomance management
Topic: Carl Love (IBM)
i is column, j is row

for(j=...)
for(i=...)
a[i][j]
will run faster than
for(i=...)
for(j=...)
a[i][j]
since the cashe won't be swapped out so much.
row major order (go by row by row)[C]
column major order (column by column) [FORTRAN]
this is language dependent.

the first way there is one cache miss then followed by 7 hits. the second has all misses so 7 more misses than the first.

4 way set associative - 4 elements in a 2 dim array fit into four cache lines

if 256 K L2 cache elements upto a(4,95) will fit into cache.

L1 cache direct mapped. 16K.

to measure it
a[N];
reg int val; // high number in M
start = time(); // real time clock
for(i=0, i< N, i++) val = a(i);
stop = time();

optimized code - compiler may throw this code away

int *a[N];
a[0] points to a[1]...a[N] points to a[1]
p = (**int)p; // forces the compiler to wait until p is set in the for loop.

int *a[N];
a[0] = a[1]...
reg int val; // high number in M
start = time(); // real time clock
for(i=0, i< N, i++) p = (**int)p;
stop = time();

time is flat at 2 cycles for array size < L1 cache size then it jumps up and is flat at 5 cycles for array size < L2 size (but not 128K due to virtual memory pages), then it goes up linearly to a max of 102 cycles then flat. Pages in memory not laid out perfectly (may be in any order) so probably not using all the L2 cache. The array size should be 2 times the size of the L2 cache to see the max time.
each cache miss costs about 95 cycles.

Linux single user mode to eliminate network

8 ints (bytes) per cache line

int a,c;
if a CPU has control of a variable it has to take control of the entire cache line that the variable is in. If the CPU has the line locked another CPU can't take it until the first one releases it.
this causes false sharing.
rewrite it as:
int a;
int junk[7];
int c;
this forces c to be in another cache line from a. junk isn't used but the space is allocated.
write programs with regard to cache line alignment.
abstraction can cause poor performance.
knowledge of the hardware and how it works and how the compiler works can help magnitudes.

check the IP every x number of clock cycles
to help find a cache miss in the program
performance counters and profilers.

look in loops and nested loops and for functions that are being called a lot.

inline macros are better than small functions

copying memory can be expensive so use assembly functions to copy blocks of memory.

Posted by lcbell4 at 7:01 PM PST
Updated: Wednesday, 2 February 2005 7:04 PM PST
Permalink
Tuesday, 16 November 2004
week 8
Planning and Scheduling
WBS
Realistic Estimating
Critical Path
Time Boxes & Critical chain

Make sure you backup data and files. Can use Nelson if need to.

May want to use source control for experience.

High level design is like the archetecture (diagrams).

A schedule will help you determine what depends on something else so you know what order to do things.

Make a stretch goal in case you have time to do more.

Make sure you have a glossary.


Posted by lcbell4 at 7:26 PM PST
Updated: Tuesday, 16 November 2004 7:39 PM PST
Permalink
Stuff to work on
Past Due
SQAP
WBS
Sequence Diagram
UI Prototype (low fidelity)
Use Cases
Class Diagram

Due 11/30/04
Unit Test Plans
High Level Design
Schedule (Schedule.xls)
updated top 10 risks
User Docs first draft
UI Prototype (high fidelity)

Due 12/14/04
High risk Prototype - working prototype of most challenging risk.

Posted by lcbell4 at 6:36 PM PST
Updated: Tuesday, 16 November 2004 6:56 PM PST
Permalink
Tuesday, 2 November 2004
Week 6
Topic: Guest Speaker
Clark Ritchie
Rational Software
Defects have a life cycle
Automated Testing to make it faster
RequisitePro
XDE tester

Posted by lcbell4 at 8:07 PM PST
Permalink
Tuesday, 26 October 2004
week 5
Introduction is to communicate details to Jay. Instructions for code to execute, etc. See page 3 of the Check-off form and assessment. If can't finish the homework put that and reasons in the intro.

SQAP - Software Quality Assurance Plan. Jay has a template.
Pick out the applicable parts for my project. Don't have to implement the whole thing.

Can use Visio for Prototyping.

Preston Smith's Risk Model
Risk Management

Posted by lcbell4 at 8:28 PM PDT
Permalink
Tuesday, 19 October 2004
Week 4
Topic: Assignment 2
Notebooks due 11/2/04 with the following:
1) Requirements
2) Use Cases
3) Test Plan
4) Risks
5) Architecture (Pass 1)

Test Plans (SQAP)

Posted by lcbell4 at 8:21 PM PDT
Updated: Tuesday, 19 October 2004 8:22 PM PDT
Permalink
week 4
Clark Ritchie Rational Software
Waterfall model Waterfall Model
Need to minimize risk at the beginning of the project.
Spiral model
What do you do at the beginning of the lifecycle? How many requirements? How big of a piece? No guidance exists for this model.
Iterative Development
Rational Unified Process download
Use case

Posted by lcbell4 at 8:00 PM PDT
Permalink
Tuesday, 12 October 2004
week 3
Topic: week 3
Need to develop Use cases and interface prototype.
Need a software engineering process or methodology.

Do a high risk interface prototype.

CRUD, Create, Read, Update, Delete (Use Cases)

Posted by lcbell4 at 6:29 PM PDT
Updated: Tuesday, 12 October 2004 8:13 PM PDT
Permalink
Tuesday, 5 October 2004
week 2
Topic: Requirements and Use Case
Requirements
.Goals
..Understand the user's needs
..Define the system
..Manage the scope and manage change
..Refine the system definition
..Build the right system
.What is it?
..A goal or objective
..A software capability needed by the user to solve a problem that will achieve an objective.
..A goal for the project that you can check off your list when you are done.
..If you don't write a test case it might not be a req't.
.Characteristics
..Traceable
..Numbered
.The most difficult part of requirements gathering is not the act of recording what the users want. It is the exploratory, developmental activity of helping users figure out what they want.
.McConnell's Process
..1. Identify key users
..2. Interview users to create a preliminary set of req'ts
..3. Create a simple, interactive prototype
more
.Asking
..Clarifying
..Inverviewing
..Interrogating
.Telling
..Asserting
..Explaining
..Dictating
.Generating
..Skillfull discussion
..Dialogue
..Politicking - giving the impression that you listen but are closed mind.
.Stay away from Telling.

Use Cases
Use cases do not include:
- User interface descriptions. This is what hte UI prototype is for.

Posted by lcbell4 at 7:11 PM PDT
Updated: Tuesday, 5 October 2004 8:38 PM PDT
Permalink
Tuesday, 28 September 2004
Week 1
First class.
We need to make two Project notebooks.
We need a Project log Larry's Project Journal
Here is a link to the CST412 web site www.oitpdx.info

Links for others

Posted by lcbell4 at 6:06 PM PDT
Updated: Saturday, 2 October 2004 3:54 PM PDT
Permalink

Newer | Latest | Older